Approaches to PCM Switching General. A digital switch's architecture is made up of two elements, called T and S, for time-division switching (T) and space-division switching (S), and can be made up of sequences of T and S. For example, the AT&T No. 4 ESS is a TSSSST switch; No. 3 EAX is an SSTSS; and the classic Northern Telecom DMS-100 is TSTS-folded. Many of these switches (e.g., DMS-100) are still available.

One thing these switches have in common is that they had multiple space (S) stages. This has now changed. Many of the new switches, or enhanced versions of the switches just mentioned, have very large capacities (e.g., 100,000 lines) and are simply TST or STS switches.

We will describe a simple time switch, a space switch, and methods of making up an architecture combining T and S stages. We will show that designing a switch with fairly high line and trunk capacity requires multiple stages. Then we will discuss the "new look" at the time stage. Time Switch. On a conceptual basis, Figure 6.16 shows a time-switch or time-slot interchanger (TSI). A time slot is the 8-bit PCM word. Remember, it expresses the voltage value of a sample taken at a certain moment in time. Of course, a time slot consists of 8 bits. A time-slot represents one voice channel, and the time slot is repeated

13VHSIC stands for very high speed integrated circuit.

Figure 6.16 A time-division switch, which we call a time-slot interchanger (TSI). Connectivity shown is from user C in the incoming slot C to user G in outgoing slot G.

Figure 6.16 A time-division switch, which we call a time-slot interchanger (TSI). Connectivity shown is from user C in the incoming slot C to user G in outgoing slot G.

8000 times a second (with different binary values of course). DS1 has 24 time slots in a frame, one for each channel. E1 has 32 time slots.

The time duration of an 8-bit time slot in each case is (125 ^sec)/24 = 5.2083 ^sec for the DS1 case, and (125 ^sec)/32 = 3.906 ^sec for the E1 case. Time-slot interchanging involves moving the data contained in each time slot from the incoming bit stream to an outgoing bit stream, but with a different time-slot arrangement in the outgoing stream, in accordance with the destination of each time slot. What is done, of course, is to generate a new frame for transmission at the appropriate switch outlet.

Obviously, to accomplish this, at least one time slot must be stored in memory (write) and then called out of memory in a changed position (read). The operations must be controlled in some manner, and some of these control actions must be kept in memory together with the software managing such actions. Typical control functions are timeslot "idle" or "busy." Now we can identify three of the basic functional blocks of a time switch:

1. Memory for speech

2. Memory for control and

3. Time-slot counter or processor

These three blocks are shown in Figure 6.17. There are two choices in handling a time switch: (1) sequential write, random read, as illustrated in Figure 6.17a, and (2) the reverse, namely, random write, sequential read as shown in Figure 6.17b. In the first case, sequential write, the time slots are written into the speech memory as they appear in the incoming bit stream. They are read out of the memory in the correct order for the outgoing bit stream.

For the second case, random write (Figure 6.17b), the incoming time slots are written into memory in the order of appearance in the outgoing bit stream. This means that the incoming time slots are written into memory in the desired output order. The writing of incoming time slots into the speech memory can be controlled by a simple time-slot counter and can be sequential (e.g., in the order in which they appear in the incoming bit stream, as in Figure 6.17a). The readout of the speech memory is controlled by the control memory. In this case the readout is random where the time slots are read out in the desired output order. The memory has as many cells as there are time slots. For the DS1 example there would be 24 cells. This time switch, as shown, works well for a single inlet-outlet switch. With just 24 cells, it can handle 23 stations besides the calling subscriber, not an auspicious number.

How can we increase a switch's capacity? Enter the space switch (S). Figure 6.18 affords a simple illustration of this concept. For example, time slot B1 on the B trunk is moved to the Z trunk into time slot Z1; and time slot Cn is moved to trunk W into time-slot Wn. However, the reader should note that there is no change in the time-slot position.

Figure 6.17a Time-slot interchange: time switch (T). Sequential write, random read.

Figure 6.17b Time-switch, time-slot interchange (T). Random write, sequential read. Space Switch. A typical time-division space switch (S) is shown in Figure 6.19. It consists of a cross-point matrix made up of logic gates that allow the switching of time slots in a spatial domain. These PCM time slot bit streams are organized by the switch into a pattern determined by the required network connectivity. The matrix consists of a number of input horizontals and output verticals with a logic gate at each cross point. The array, as shown in the figure, has M horizontals and N verticals, and

Sts And Tst Switching
Figure 6.18 Space switch connects time slots in a spatial configuration.
Figure 6.19 Time-division space switch cross-point array showing enabling gates.

we call it an M x N array. If M = N, the switch is nonblocking; If M > N, the switch concentrates, and if M < N, the switch expands.

Return to Figure 6.19. The array consists of a number of (M) input horizontals and (N) output verticals. For a given time slot, the appropriate logic gate is enabled and the time slot passes from the input horizontal to the desired output vertical. The other horizontals, each serving a different serial stream of time slots, can have the same time slot (e.g., a time slot from time slots number 1-24, 1-30, or 1-n; e.g., time slot 7 on each stream) switched into other verticals enabling their gates. In the next time-slot position (e.g., time slot 8), a completely different path configuration could occur, again allowing time slots from horizontals to be switched to selected verticals. The selection, of course, is a function of how the traffic is to be routed at that moment for calls in progress or being set up.

The space array (cross-point matrix) does not switch time slots as does a time switch (time-slot interchanger). This is because the occurrences of time slots are identical on the horizontal and on the vertical. It switches in the space domain, not in the time domain. The control memory in Figure 6.19 enables gates in accordance with its stored information.

If an array has M inputs and N outputs, M and N may be equal or unequal depending on the function of the switch on that portion of the switch. For a tandem or transit switch we would expect M = N. For a local switch requiring concentration and expansion, M and N would be unequal.

If, in Figure 6.19, it is desired to transmit a signal from input 1 (horizontal) to output 2 (vertical), the gate at the intersection would be activated by placing an enable signal on S12 during the desired time-slot period. Then the eight bits of that time slot would pass through the logic gate onto the vertical. In the same time slot, an enable signal on SM1 on the Mth horizontal would permit that particular time slot to pass to vertical 1. From this we can see that the maximum capacity of the array during any one time-slot interval measured in simultaneous call connections is the smaller value of M or N. For example, if the array is 20 x 20 and a time-slot interchanger is placed on each input (horizontal) line and the interchanger handles 30 time slots, the array then can serve 20 x 30 = 600 different time slots. The reader should note how the TSI multiplies the call-handling capability of the array when compared with its analog counterpart. Time-Space-Time Switch. Digital switches are composed of time and space switches in any order.14 We use the letter T to designate a time-switching stage and use S to designate a space-switching stage. For instance, a switch that consists of a sequence of a time-switching stage, a space-switching stage, and a time-switching stage is called a TST switch. A switching consisting of a space-switching stage, a time-switching stage, and a space-switching stage is designated an STS switch. There are other combinations of T and S. As we mentioned earlier, the AT&T No. 4 ESS switch is a good example. It is a TSSSST switch.

Figure 6.20 illustrates the time-space-time (TST) concept. The first stage of the switch is the TSI or time stages that interchange time slots (in the time domain) between external incoming digital channels and the subsequent space stage. The space stage provides connectivity between time stages at the input and output. It is a multiplier of call-handling capacity. The multiplier is either the value for M or value for N, whichever is smaller. We also saw earlier that space-stage time slots need not have any relation to either external incoming or outgoing time slots regarding number, numbering, or position. For instance, incoming time slot 4 can be connected to outgoing time slot 19 via space network time slot 8.

If the space stage of a TST switch is nonblocking, blocking in the overall switch occurs if there is no internal space-stage time slot during which the link from the inlet time stage and the link to the outlet time stage are both idle. The blocking probability can be minimized if the number of space-stage time slots is large. A TST switch is strictly nonblocking if l = 2c - 1, (6.1)

14The order is a switch designer's decision.

Tst Switch With Block Diagram
Figure 6.20 A time-space-time (TST) switch. TSI = time-slot interchanger.

where l is the number of space-stage time slots and c is the number of external TDM time slots (Ref. 3). Space-Time-Space Switch. A space-time-space switch reverses the order architecture of a TST switch. The STS switch consists of a space cross-point matrix at the input followed by an array of time-slot interchangers whose ports feed another cross-point matrix at the output. Such a switch is shown in Figure 6.21. Consider this operational example with an STS. Suppose that an incoming time slot 5 on port No. 1 must be connected to an output slot 12 at outgoing port 4. This can be accomplished by time-slot interchanger No. 1, which would switch it to time slot 12; then the outgoing space stage would place that on outgoing trunk No. 4. Alternatively, time slot 5 could be placed at the input of TSI No. 4 by the incoming space switch, where it would be switched to time slot 12, and then out port No. 4.

Space stage Time stage Space stage

Space stage Time stage Space stage

Figure 6.21 A space-time-space switch. TST Compared with STS. Both TST and STS switches can be designed with identical call-carrying capacities and blocking probabilities. It can be shown that a direct one-to-one mapping exists between time-division and space-division networks (Ref. 3).

The architecture of TST switching is more complex than STS switching with space concentration. The TST switch becomes more cost-effective because time expansion can be achieved at less cost than space expansion. Such expansion is required as link utilization increases because less concentration is acceptable as utilization increases.

It would follow, then, that TST switches have a distinct implementation advantage over STS switches when a large amount of traffic must be handled. Bellamy (Ref. 3) states that for small switches STS is favored due to reduced implementation complexities. The choice of a particular switch architecture may be more dependent on such factors as modularity, testability, and expandability.

One consideration that generally favors an STS implementation is the relatively simpler control requirements. However, for large switches with heavy traffic loads, the implementation advantage of the TST switch and its derivatives is dominant. A typical large switch is the ATT No. 4 ESS, which has a TSSSST architecture and has the capability of terminating 107,520 trunks with a blocking probability of 0.5% and channel occupancy of 0.7.

+1 -1

Post a comment